1. Field of the Invention
The invention relates generally to the field of clock buffer circuits and more specifically to those circuits which buffer multiple phase clock signals.
2. Description of the Prior Art
In digital devices, particularly in microprocessors and other devices in which various operations must be synchronized, global clock or timing signals are used to synchronize the various circuits within the device. The conductors, or lines, carrying the clock signals are often quite lengthy, as they must extend throughout the devices to all of the various circuits which must be synchronized. Because the lengths of the lines which carry the timing signals and the number of circuit elements driven by the timing signals result in large capacitive loads for the circuits which generate the clocking signals, those circuits must be able to provide large amounts of current to ensure that the clock signals have fast rising and falling edge rates. The problem is particularly acute in integrated circuit chips, since it is desired to keep the active devices as small as possible, which limits the amount of current available from the devices.
Typically, timing signals are initially generated by a flip-flop or a set of flip-flops connected to generate inter-related multiple-phase output signals. Since flip-flops of the switching speed required for the clock signals of current microprocessors typically cannot also provide the currents required for the fast rise and fall times, the output signals from the flip-flops are transmitted as enabling signals to a buffer circuit, which includes transistors large enough to produce clocking signals having the required currents. The output signals from the buffer circuit comprise the clock signals which are transmitted to the various synchronized circuits throughout the device.
Since the clock buffer circuit must provide large amounts of current, the clock buffer can take up a significant portion of the area of chips designed using very large scale integration techniques. The problem of providing a clock buffer circuit on such chips is greatly magnified when, as is the case with many microprocessors, the clock circuit must provide clock signals of several different phases all of which are themselves synchronized. Not only must the flip-flops providing the enabling signals be synchronized, the buffer circuits must also be synchronized to ensure that the generated clocking signals have the required rise and fall characteristics with respect to each other.
In prior clock circuits, the clock buffer circuits used bootstrapping techniques to boost the voltage level of the output signal of the buffer circuit to a desired nominal output voltage. In such bootstrapping techniques, pull-up and pull-down field effect transistors are connected in series between a positive power supply and ground. A bootstrap capacitor is connected to the gate terminal of the pull-up transistor and the output clock signal is taken from the node between the two transistors. The enabling signal is applied to the gate of the pull-up transistor. When the clocking signal is at ground level, the pull-down transistor is turned on and the pull-up transistor is turned off. The enabling signal from the flip-flop clock signal generator begins to rise, which turns the pull-up transistor on, when the clocking signal is to rise. Since both the pull-up and pull-down transistors at this point are conducting, a condition known as "overlap", the voltage level of the clocking signal increases slightly above ground. The capacitor connected to the gate of the pull-up transistor is charged during this period. The gate of the pull-up transistor is then isolated and the pull-down transistor is turned off, which causes the voltage level of the gate of the pull-up transistor to rise above the power supply voltage level and the voltage level of the node between the transistors, from which the clocking signal is taken, to increase to the power supply voltage level.
The prior bootstrap techniques had a number of problems, however. The overlap current, that is, the current flowing through the pull-up and pull-down transistors when they were both conducting, was quite large. Furthermore, the required bootstrap capacitors occupied large amounts of chip area, which reduced the amount of chip area available for other circuits.
Furthermore, since the pull-up transistor was driven into saturation, electrons in the transistor's channel were subject to a high electric field associated with the high drain to source voltage accompanying saturation, which could accelerate them into the substrate and or cause tunnelling into the gate oxide insulating the gate terminal from the substrate, so-called "hot electron" problems. The electrons driven into the substrate caused noise problems in signals throughout the rest of the chip, while electrons tunnelling into the gate oxide caused a degradation in the operation of the transistor by increasing the threshold voltage required to turn the transistor on. Since this degradation occurred over, and varied with, time, and also varied from transistor to transistor, the reliability of the chip would undergo a steady and unpredictable deterioration.